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The Advanced Warfare Technology Division (AWT) of the Leidos Innovations Center (LInC) is looking for a Hardware Design Engineer to work with a multi-disciplined design team (electrical & mechanical engineers, systems engineers, software engineers, etc.) to design, develop, simulate, and integrate challenging circuit card designs for DSP and RF sensor systems based on given project requirements. Candidate will have a strong hardware background in high-speed digital circuit design, schematic entry, printed-circuit board fabrication, and conduction-cooled circuit card assembly design, in support of a fast paced, multi-disciplinary design team. This role will also support integration, test, and verification in the final products.
Primary Responsibilities:
Collaborate with a multi-disciplined engineering design team to design, test and integrate sophisticated digital designs hardware and firmware including RF sensor systems.
Review and analyze high level system requirements, participate in defining, deriving and allocating these requirements into lower-level hardware requirements.
Translate conceptual designs into design specifications and implement within detailed electrical designs involving electrical schematics, complete bills of materials (BOMs), Printed Circuit Board Design (PCB), layout techniques, documents and fabrication drawings.
Analyze, design, develop and test embedded electronic circuit card assemblies (CCA’s) containing Programmable Logic Devices (RFSoC, SoC, FPGA), data conversation, signal processing/filtering, high speed digital and analog, RF & amplification, power supply & power management circuitry.
Analyze schematic diagrams for either custom or commercial-off-the shelf (COTS) electronic hardware involving high-speed digital and/or analog circuitry in associated FPGA-centric systems.
Analyze, design, simulate, and implement designs which interface to common high-speed signaling standards such as SERDES, PLLs, and/or protocols such as PCIe Gen4, JESD204B/C, LVDS, etc.
Evaluate, select, specify, design, modify, test, and/or integrate sensors, electronic modules (custom and COTS), cables, connectors, power subsystems.
Apply basic knowledge of HDL design using VHDL/Verilog to write, simulate, synthesize and test designs used within various logic devices (SoC,FPGA/CPLD).
Conduct experimental tests on equipment, evaluate results, followed by specification development for selecting components and equipment for deliverable systems.
Generate and maintain requirements documents, functional specification documents, interface control documents and engineering drawings while applying configuration management policies.
Develop project test plans and test procedures, provide test planning support, assist in the execution of both lab testing and field testing.
Provide field support planning, mobilization/de-mobilization support, and other field support in general.
Interact with outside customers, suppliers, and functional peer groups.
Provide status reports to project managers and/or project lead as required.
Some travel and work at remote sites for limited time periods will be required.
Basic Qualifications:
BS in Electrical Engineering or Computer Engineering or related degree
Minimum of 4 years of relevant experience
Ability to be granted a security clearance
Able to work and collaborate within a multidisciplinary engineering environment.
Strong debug and problem-solving skills
Familiarity or experience with one or more of the following:
Schematic entry / PCB design tools (Altium, Cadence Allegro/OrCAD, KiCAD, or similar)
Printed Circuit Board (PCB) Design involving parts selection, BOM creation, placement, high speed signal routing, fabrication drawings and documentation.
HDL Design / Development (VHDL/Verilog) with System-On-Chip devices (SOC’s), FPGA’s, CPLD/s, and/or Microcontrollers.
Vendor Design tools and Design Environments (IDE’s) such as Xilinx Vivado, Vitis, Quartus, Questa Sim, Libero, Synplicity, etc.
Lab test equipment – Oscilloscope, Voltmeter, Logic Analyzer, Spectrum Analyzer
Revision control (git, SVN, ClearCase, etc.)
Interfaces: DDRx, ADC/DACs, SerDes, PCIe, JTAG
Hands on Lab testing and Integration
Preferred Qualifications:
Master’s Degree in Electrical or Computer Engineering
Existing Secret (or above) Clearance
Experience supporting or leading different phases of the product development lifecycle, including requirements analysis, system design, product development, integration, test, technical documentation and review of complex systems.
Design, testing, integration and troubleshooting electronic circuits within embedded systems including digital, analog and radio frequency (RF) subsystems.
Working Experience with the following:
High speed PCB design techniques (> 1GHz)
DSP fundamentals and FPGA implementation
Schematic/PCB design tools such as Altium Designer, Cadence Allegro/OrCAD or KiCAD, or similar.
Simulation / Validation and Designer-Level Testbench generation (VHDL/SystemVerilog) – using vendor tools or third party (Xilinx simulator, Siemens Modelsim/Questa, etc.)
Script Generation (Perl, TCL, Python, etc)
Microchip EDA tools and flows (Synopsys, Cadence, etc.)
System Verilog / UVM
High speed protocols like JESD204B, LVDS, PCIe, SERDES
Performance characteristics of Analog Data Converters (ADCs/DACs)
Digital Signal Processing (DSP) modeling using tools like MATLAB/Simulink
C/C language software development for embedded, real-time systems
AWTLINC
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For U.S. Positions: While subject to change based on business needs, Leidos reasonably anticipates that this job requisition will remain open for at least 3 days with an anticipated close date of no earlier than 3 days after the original posting date as listed above.
The Leidos pay range for this job level is a general guideline only and not a guarantee of compensation or salary. Additional factors considered in extending an offer include (but are not limited to) responsibilities of the job, education, experience, knowledge, skills, and abilities, as well as internal equity, alignment with market data, applicable bargaining agreement (if any), or other law.